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low power, selectable gain differential adc driver, g = 1, 2, 3 data sheet ada4950 - 1 / ada4950 - 2 rev. b document feedback information furnished by analog devices is believed to be accurate and reliable. ho wever, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2009 C 2015 analog devices, inc. all rights reserved. technical support www.analog.com features high performance at low power high speed ?3 db bandwidth of 750 m hz, g = 1 0.1 db flatness to 210 mhz , v out, dm = 2 v p - p, r l, dm = 200 slew rate: 2 9 00 v/s, 25% to 75% fast 0.1% settling time of 9 ns low power: 9.5 ma per amplifier low harmonic distortion 108 db sfdr @ 10 mhz 9 8 db sfdr @ 20 mhz low output voltage noise: 9.2 nv/hz , g = 1, rto 0.2 mv typical input offset voltage selectable d ifferential g ains of 1, 2, and 3 d ifferential - to - differential or single - ended - to - differential operation adjust able output common - mode voltage input common - mode range shifted down by 1 v be wide supply range: + 3 v to 5 v available in 16 - lead and 24 - lead lfcsp packages applications adc drivers single - e nded - to - differential converters if and baseband gain blocks differential buffers line drivers general description the ada4950 - 1 / ada4950 - 2 are gain - selectable version s of the ada4932 - 1 / ada4932 - 2 with on - chip feedback and gain resistors . they are ideal choice s for driving high performance adcs as single - ended - to - differential or differential - to - differential amplifier s . the output common - mode voltage is user adjustable by means of an internal common - mode feedback loop, allowing the ada4950 - 1 / ada4950 - 2 output to match the input of the adc. the internal feedback loop also provides exceptional output balance as well as suppression of even - order harmonic distortion products . d ifferential gain configurations of 1, 2, and 3 are easily realized with internal feedback network s that are connected externally to set the cl osed - loop gain of the amplifier . the ada4950 - 1 / ada4950 - 2 are fabricated using the analog devices, inc., propri etary silicon - germanium (sige) complementary bipolar process, enabling them to achieve low levels of distortion and noise at low power consumption . the low offset and excellent dynamic performance of the ada4950 - x make it well suited for a wide variety of data acquisition and signal processing applications. functional block diagram s +inb +in a ?in a ?inb ?out pd +out v ocm +v s +v s +v s +v s ?v s ?v s ?v s ?v s 07957-001 12 1 1 10 1 3 4 9 2 6 5 7 8 16 15 14 13 ada4950-1 figure 1. ada4950 - 1 07957-002 2 1 3 4 5 6 18 17 16 15 14 13 +ina2 + inb2 +v s1 +v s1 ? inb 1 ?ina1 ?out2 pd2 ?v s2 ?v s2 v ocm1 +out1 8 9 10 11 7 ?inb2 +v s2 +v s2 v ocm2 12 +out2 ?ina2 20 19 21 pd1 ?out1 ?v s1 22 ?v s1 23 +inb1 24 +ina1 ada4950-2 figure 2. ada4950 - 2 ?14 0 ? 13 0 ?12 0 ?11 0 ?10 0 ?9 0 ? 8 0 ?7 0 ?6 0 ?5 0 ?4 0 harmonic distortion (dbc) f r e q u e nc y ( m h z ) v o u t , dm = 2 v p-p 0. 1 1 1 0 10 0 hd2, 5v hd3, 5v hd2, 2.5v hd3, 2.5v 07957-025 figure 3 . harmonic distortion vs. frequency at various supplies the devices are available in a pb - free, 3 mm 3 mm, 16- lead lfcsp ( ada4950 - 1 , single) or a pb - free, 4 mm 4 mm , 24- lead lfcsp ( ada4950 - 2 , dual). the pinout ha s been optimized to facilitate pcb layout and minimize distortion. the ada4950 - 1 / ada4950 - 2 are specified to operate over the ?40 c to +105c temperature range; both operate on supplies from +3 v to 5 v .
ada4950- 1/ada4950 - 2 data s heet rev. b | page 2 of 26 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general descript ion ......................................................................... 1 functional block diagrams ............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 5 v operation ............................................................................. 3 5 v operation ............................................................................... 5 absolute maximum ratings ............................................................ 7 thermal resistance ...................................................................... 7 maximum po wer dissipation ..................................................... 7 esd caution .................................................................................. 7 pin configurations and function descriptions ........................... 8 typical performance characteristics ............................................. 9 test circuits ..................................................................................... 16 terminology .................................................................................... 17 theory of operation ...................................................................... 18 applications information .............................................................. 19 anal yzing an application circuit ............................................ 19 selecting the closed - loop gain ............................................... 19 estimating the output noise voltage ...................................... 19 calculating the input impedance for an application circuit .......................................................................................... 20 input common - mode voltage range ..................................... 22 input and output capacitive ac coupling ............................ 22 input signal swing considerations .......................................... 22 setting the output common - mode voltage .......................... 22 layout, grounding, and bypassing .............................................. 23 high performance adc driving ................................................. 24 outline dimensions ....................................................................... 25 ordering g uide .......................................................................... 25 revision history 10/15 rev. a to rev. b changed cp - 16- 2 to cp - 16- 21 ......................................... universal changes to figure 1 .......................................................................... 1 changes to figure 5 .......................................................................... 8 updated outline dimensions ....................................................... 25 changes to ordering guide .......................................................... 25 3 /13 rev. 0 to rev. a updated outline dimensions ....................................................... 25 changes to ordering guide .......................................................... 25 5 /0 9 revision 0 : initial version
data sheet ada4950- 1/ada4950 - 2 rev. b | page 3 of 26 specifications 5 v operation t a = 25c, +v s = 5 v, ? v s = ?5 v, v ocm = 0 v , g = 1 , r t = 5 3.6 (when used), r l, dm = 1 k?, unless otherwise noted. all specifications refer to single - ended input and differential outputs, unless otherwise noted. refer to figure 52 for signal definitions. d ifferential inputs to v out, dm performance tale parameter test conditions /comments min typ max unit dynamic performance ?3 db small - signal bandwidth v out, dm = 0.1 v p -p 750 mhz ?3 db large - signal bandwidth v out, dm = 2.0 v p -p 350 mhz bandwidth for 0.1 db flatness v out, dm = 2.0 v p - p, r l = 200 ? ada4950 -1 210 mhz ada4950 -2 230 mhz slew rate v out, dm = 2 v p - p, 25% to 75% 2900 v/s settling time to 0.1% v out, dm = 2 v step 9 ns overdrive recovery time v in = 0 v to 5 v ramp, g = 2 20 ns noise/harmonic performance see figure 51 for distortion test circuit second harmonic v out, dm = 2 v p -p 1 mhz ?108 dbc 10 mhz ?107 dbc 20 mhz ?98 dbc 50 mhz ?80 dbc third harmonic v out, dm = 2 v p -p 1 mhz ?126 dbc 10 mhz ?105 dbc 20 mhz ?99 dbc 50 mhz ?84 dbc imd 3 f 1 = 30 mhz, f 2 = 30.1 mhz, v out, dm = 2 v p -p ?94 dbc voltage noise (referred to output ) f = 1 mhz gain = 1 9.2 nv/hz gain = 2 12.5 nv/hz gain = 3 16.6 nv/hz crosstalk ( ada4950 - 2 ) f = 10 mhz; channel 2 active, channel 1 output ?87 db input characteristics offset voltage (referred to input ) v +din = v ?din = v ocm = 0 v ?2.5 0.2 +2.5 mv t min to t max variation C 3.7 v/c input capacitance single - ended at package pin 0.5 pf input common - mode voltage range directly at internal amplifier inputs, not external input terminals ? v s + 0.2 to +v s ? 1.8 v cmrr dc, ?v out, dm /?v in, cm , ?v in, cm = 1 v ?64 ?49 db open - loop gain 64 66 db output characteristics output voltage swing maximum ?v out , single - ended output, r l = 1 k? C v s + 1.4 to +v s C 1. 4 ? v s + 1 .2 to +v s ? 1. 2 v linear output current 200 khz, r l, dm = 10 ?, sfdr = 6 9 db 114 ma peak output balance error ?v out, cm /?v out, dm , ?v out, dm = 2 v p - p, 1 mhz ; see figure 50 for output balance test circuit ?62 db gain error gain = 1 0.5 1.2 % gain = 2 1.0 1.9 % gain = 3 0.8 1.7 %
ada4950- 1/ada4950 - 2 data s heet rev. b | page 4 of 26 v ocm to v out, cm performance table 2 . parameter test conditions /comments min typ max unit v ocm dynamic performance ?3 db small - signal bandwidth v out, cm = 100 mv p -p 250 mhz ?3 db larg e - signal bandwidth v out, cm = 2 v p -p 105 mhz slew rate v in = 1.5 v to 3.5 v, 25% to 75% 430 v/s input voltage noise (r eferred to input ) f = 1 mhz 9.8 nv/hz v ocm input characteristics input voltage range C v s + 1.2 to +v s C 1.2 v input resistance 22 26 32 k? input offset voltage v +din = v ?din = 0 v ?6 + 0.8 +6 mv v ocm cmrr v out, dm /v ocm , v ocm = 1 v ?60 ?4 9 db gain v out, cm /v ocm , v ocm = 1 v 0.98 1.0 1.01 v/v general performance table 3 . parameter test conditions /comments min typ max unit power supply operating range 3.0 11 v quiescent current per amplifier 8.8 9.5 10.1 ma t min to t max variation 31 a/c powered down 0.7 1.0 ma power supply rejection ratio v out, dm /v s , v s = 1 v p -p ?96 ?84 db power - down ( pd ) pd input voltage powered down (+v s C 2.5) v enabled ( +v s C 1.8) v turn - off time 600 ns turn - on time 28 ns pd pin bias current per amplifier enabled pd = 5 v ?1.0 + 0.2 +1.0 a disabled pd = 0 v ?250 ?180 ?140 a operating temperature range ?40 +105 c
data sheet ada4950- 1/ada4950 - 2 rev. b | page 5 of 26 5 v operation t a = 25c, +v s = 5 v, ? v s = 0 v, v ocm = 2.5 v, g = 1 , r t = 53.6 (when used), r l, dm = 1 k?, unless otherwise noted. all specifications refer to single - ended input and differential outputs, unless otherwise noted. refer to figure 52 for signal defini tions. d ifferential inputs to v out, dm performance tale parameter test conditions /comments min typ max unit dynamic performance ?3 db small - signal bandwidth v out, dm = 0.1 v p -p 770 mhz ?3 db large - signal bandwidth v out, dm = 2.0 v p -p 320 mhz bandwidth for 0.1 db flatness v out, dm = 2.0 v p - p, r l = 200 ? ada4950 -1 220 mhz ada4950 -2 160 mhz slew rate v out, dm = 2 v p - p, 25% to 75% 2200 v/s settling time to 0.1% v out, dm = 2 v step 10 ns overdrive recovery time v in = 0 v to 2.5 v ramp, g = 2 19 ns noise/harmonic performance see figure 51 for distortion test circuit second harmonic v out, dm = 2 v p - p 1 mhz ?108 dbc 10 mhz ?107 dbc 20 mhz ?98 dbc 50 mhz ?82 dbc third harmonic v out, dm = 2 v p -p 1 mhz ?124 dbc 10 mhz ?114 dbc 20 mhz ?99 dbc 50 mhz ?83 dbc imd 3 f 1 = 30 mhz, f 2 = 30.1 mhz, v out, dm = 2 v p -p ?94 dbc voltage noise ( referred to input ) f = 1 mhz gain = 1 9.2 nv/hz gain = 2 12.5 nv/hz gain = 3 16.6 nv/hz crosstalk ( ada4950 -2 ) f = 10 mhz ; channel 2 active, channel 1 output ?87 db input characteristics offset voltage ( referred to input ) v +din = v ?din = v ocm = 2.5 v ?4 0.4 +4 mv t min to t max variation ?3.7 v/c input capacitance single - ended at package pin 0.5 pf input common - mode voltage range directly at internal amplifier inputs, not external input terminals C v s + 0.2 to +v s C 1.8 v cmrr dc, ?v out, dm /?v in, cm , ?v in, cm = 1 v ?64 ?49 db open - loop gain 64 66 db output characteristics output voltage swing maximum ?v out , single - ended output, r l = 1 k? C v s + 1 .2 to +v s C 1. 2 C v s + 1.1 to +v s C 1. 1 v linear output current 200 khz, r l, dm = 10 ?, sfdr = 67 db 70 ma peak output balance error ?v out, cm /?v out, dm , ?v out, dm = 1 v p - p, 1 mhz ; see figure 50 for output balance test circuit ?62 db gain error gain = 1 0.5 1.2 % gain = 2 1.0 1.9 % gain = 3 0.8 1.7 %
ada4950- 1/ada4950 - 2 data s heet rev. b | page 6 of 26 v ocm to v out, cm performance table 5 . parameter test conditions /comments min typ max unit v ocm dynamic performance ?3 db small - signal bandwidth v out, cm = 100 mv p -p 240 mhz ?3 db large - signal bandwidth v out, cm = 2 v p -p 90 mhz slew rate v in = 1.5 v to 3.5 v, 25% to 75% 380 v/s input voltage noise ( referred to input) f = 1 mhz 9.8 nv/hz v ocm input characteristics input voltage range C v s + 1.2 to +v s C 1.2 v input resistance 22 26 32 k? input offset voltage v +din = v ?din = 2.5 v ?6.5 + 1.0 +6.5 mv v ocm cmrr v out, dm /v ocm , v ocm = 1 v ?60 ?4 9 db gain v out, cm /v ocm , v ocm = 1 v 0.98 1.0 1.01 v/v general performance table 6 . parameter test conditions /comments min typ max unit power supply operating range 3.0 11 v quiescent current per amplifier 8.4 8.9 9.6 ma t min to t max variation 31 a/c powered down 0.6 0.9 ma power supply rejection ratio v out, dm /v s , v s = 1 v p -p ?96 ?84 db power - down ( pd ) pd input voltage powered down (+v s C 2.5) v enabled (+v s C 1.8) v turn - off time 600 ns turn - on time 29 ns pd pin bias current per amplifier enabled pd = 5 v ?1.0 + 0.2 +1.0 a disabled pd = 0 v ?100 ?65 ?40 a operating temperature range ?40 +105 c
data sheet ada4950- 1/ada4950 - 2 rev. b | page 7 of 26 absolute maximum rat ings table 7 . parameter rating supply voltage 11 v power dissipation see figure 4 input current, +in x , ? in x , pd 5 ma storage temperature range ?65c to +125c operating temperature range ada4950 -1 ?40c to +105c ada4950 -2 ?40c to +105c lead temperature (soldering, 10 sec) 300c junction temperature 150c stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the o perational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. thermal resistance ja is specified for the device (including exposed pad) soldered to a high thermal conductivity 2s2p printed circuit board, as described in eia/jesd51 - 7. table 8 . thermal resistance package type ja j c unit ada4950 -1 , 16 - lead lfcsp (exposed pad) 91 28 c/w ada4950 -2 , 24 - lead lfcsp (exposed pad) 65 16 c/w maximum power dissip ation the maximum safe power dissipation in the ada4950 - x package is limited by the associated rise in junction temperature (t j ) on the die. at approximately 150c, which is the glass transition temperature, the plastic changes its properties. even temporarily e xceeding this temperature limit can change the stresses that the package exerts on the die, permanently shifting the parametric performanc e of the ada4950 - x . exceeding a junction temper - a ture of 150c for an extended period can result in changes in the sil icon devices, potentially causing failure. the power dissipated in the package (p d ) is the sum of the quies - cent power dissipation and the power dissipated in the package due to the load drive. the quiescent power is the voltage between the supply pins ( v s ) times the quiescent current (i s ). the power dissipated due to the load drive depends upon the particular application. the power dissipated due to the load drive is calcu - lated by multiplying the load current by the associated voltage drop across the device. rms voltages and currents must be used in these calculations. airflow increases heat dissipation, effectively reducing ja . in addition, more metal directly in contact with the package leads/ exposed pad from metal traces, through holes, ground, an d power planes reduces ja . figure 4 shows the maximum safe power dissipation in the package vs. the ambient temperature for the single 1 6 - lead lfcsp ( 91 c/w) and the dual 24 - lead lfcsp ( 65 c/w) on a jedec standard 4 - layer board with the exposed pad soldered to a pcb pad that is connected to a solid plane . 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 ?40 ?20 0 20 40 07957-004 60 80 100 ambient temperature (c) maximum power dissipation (w) ada4950-2 ada4950-1 figure 4 . maximum power dissipation vs. ambient temperature for a 4 - layer board esd caution
ada4950- 1/ada4950 - 2 data s heet rev. b | page 8 of 26 pin configuration s and function descrip tions notes 1. solder the exposed paddle on the back of the package to a ground plane or to a power plane. +inb +ina ?ina ?inb ?out pd +out v ocm +v s +v s +v s +v s ?v s ?v s ?v s ?v s 07957-005 12 1 1 10 1 3 4 9 2 6 5 7 8 16 15 14 13 ada4950-1 t op view (not to scale) figure 5. ada4950 - 1 pin configuration 07957-006 2 1 3 4 5 6 18 17 16 15 14 13 +ina2 + inb2 +v s1 +v s1 ? inb 1 ?ina1 ?out2 pd2 ?v s2 ?v s2 v ocm1 +out1 8 9 10 11 7 ?inb2 +v s2 +v s2 v ocm2 12 +out2 ?ina2 20 19 21 pd1 ?out1 ?v s1 22 ?v s1 23 +inb1 24 +ina1 ada4950-2 top view (not to scale) notes 1. solder the exposed paddle on the back of the package to a ground plane or to a power plane. figure 6. ada4950 - 2 pin configuration table 9 . ada4950 - 1 pin function description s pin no. mnemonic description 1 +inb positive input b , 250 ? input. use alone for g = 2 or tie to +ina for g = 3. 2 +ina positive input a , 500 ? input. use alone for g = 1 or tie to +in b for g = 3. 3 ? ina negative input a , 500 ? input. use alone for g = 1 or tie to ?inb for g = 3. 4 ? inb negative input b , 250 ? input. use alone for g = 2 or tie to ? ina for g = 3. 5 to 8 +v s positive supply v oltage . 9 v ocm output common - mode voltage . 10 +out positive output . 11 ?out negative output . 12 pd power - down pin . 13 to 16 ?v s negative supply voltage . 17 (epad) exposed paddle (epad) solder the exposed paddle on the back of the package to a ground plane or to a power plane . table 10. ada4950 -2 pin function descriptions pin no. mnemonic description 1 ? ina1 negative input a, amplifier 1 , 500 ? input. use alone for g = 1 or tie to C inb1 for g = 3. 2 ? inb1 negative input b, amplifier 1 , 250 ? input. use alone for g = 2 or tie to C ina1 for g = 3. 3, 4 +v s1 positive supply voltage , amplifier 1 . 5 +inb2 positive input b, amplifier 2 , 250 ? input. use alone for g = 2 or tie to +ina2 for g = 3. 6 +ina2 positive input a, amplifier 2 , 500 ? input. use alone for g = 1 or tie to +inb2 for g = 3. 7 ? ina2 negative input a, amplifier 2 , 500 ? input. use alone for g = 1 or tie to C inb2 for g = 3. 8 ? inb2 negative input b, amplifier 2 , 250 ? input. use alone for g = 2 or tie to C ina2 for g = 3. 9, 10 +v s2 positive supply voltage , amplifier 2 . 11 v ocm2 output common - mode voltage , amplifier 2 . 12 +out2 positive output , amplifier 2 . 13 ?out2 negative output , amplifier 2 . 14 pd2 power - down pin , amplifier 2 . 15, 16 ?v s2 negative supply voltage , amplifier 2 . 17 v ocm1 output common - mode voltage , amplifier 1 . 18 +out1 positive output , amplifier 1 . 19 ?out1 negative output , amplifier 1 . 20 pd1 power - down pin , amplifier 1 . 21, 22 ?v s1 negative supply voltage , amplifier 1 . 23 +inb1 positive input b, amplifier 1 , 250 ? input. use alone for g = 2 or tie to +ina1 for g = 3. 24 +ina1 positive input a, amplifier 1 , 500 ? input. use alone for g = 1 or tie to +inb1 for g = 3. 25 (epad) exposed paddle (epad) solder the exposed paddle on the back of the package to a g round plane or to a power plane .
data sheet ada4950- 1/ada4950 - 2 rev. b | page 9 of 26 typical performance characteristics t a = 25c, +v s = 5 v, ? v s = ?5 v , v ocm = 0 v , g = 1 , r t = 5 3 .6 ? (when used) , r l, dm = 1 k?, unless otherwise noted. refer to figure 49 for test setup. refer to figure 52 for signal definitions. ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 1 10 100 frequenc y (mhz) 1000 07957-007 normalized closed-loo p gain (db) v ou t , dm = 100mv p-p g = 1, r t = 53.6? g = 2, r t = 57.6? g = 3, r t = 61.9? figure 7 . small - signal frequency response for various gains ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 1 10 100 frequenc y (mhz) 1000 07957-008 closed-loo p gain (db) v s = 5v v s = 2.5v v ou t , dm = 100mv p-p figure 8. small - signal frequency response for various supplies ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 1 10 100 frequenc y (mhz) 1000 07957-009 closed-loo p gain (db) t a = ?40c t a = +25c t a = +105c v ou t , dm = 100mv p-p figure 9. small - signal frequency response for various temperatures ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 1 10 100 1000 07957-010 normalized closed-loo p gain (db) v ou t , dm = 2v p-p g = 1, r t = 53.6? g = 2, r t = 57.6? g = 3, r t = 61.9? frequenc y (mhz) figure 10 . large - signal frequency respo nse for various gains ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 1 10 100 1000 07957-0 1 1 closed-loo p gain (db) v ou t , dm = 2v p-p v s = 5v v s = 2.5v frequenc y (mhz) figure 11 . large - signal frequency response for various supplies ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 1 10 100 1000 07957-012 closed-loo p gain (db) frequenc y (mhz) v ou t , dm = 2v p-p t a = ?40c t a = +25c t a = +105c figure 12 . large - signal frequency response for various temperatures
ada4950- 1/ada4950 - 2 data s heet rev. b | page 10 of 26 1 10 100 1000 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 07957-013 closed-loo p gain (db) frequenc y (mhz) v ou t , dm = 100mv p-p r l = 1k? r l = 200? figure 13 . small - signal frequency response at various loads ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 1 10 100 frequenc y (mhz) 1000 07957-014 closed-loo p gain (db) v ou t , dm = 100mv p-p v ocm = ?2.5vdc v ocm = 0v v ocm = +2.5vdc figure 14 . small - signal frequency response for vario us v ocm levels 1 10 100 frequenc y (mhz) 1000 07957-015 closed-loo p gain (db) v ou t , dm = 100mv p-p ?8 ?6 ?4 ?2 0 2 4 c l = 0pf c l = 0.9pf c l = 1.8pf c l = 2.7pf figure 15 . small - signal frequency response at various capacitive loads ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 1 10 100 1000 07957-016 closed-loo p gain (db) v ou t , dm = 2v p-p r l = 1k? r l = 200? frequenc y (mhz) figure 16 . large - signal frequency response at various loads ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 1 10 100 frequenc y (mhz) 1000 07957-017 closed-loo p gain (db) v ou t , dm = 2v p-p v ocm = ?2.5vdc v ocm = 0v v ocm = +2.5vdc figure 17 . large - signal frequency response for various v ocm levels ?8 ?6 ?4 ?2 0 2 4 1 10 100 1000 07957-018 closed-loo p gain (db) frequenc y (mhz) v ou t , dm = 2v p-p c l = 0pf c l = 0.9pf c l = 1.8pf c l = 2.7pf figure 18 . large - signal frequency response at various capacitive loads
data sheet ada4950- 1/ada4950 - 2 rev. b | page 11 of 26 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 1 10 100 1000 closed-loop gain (db) 07957-019 v ou t , dm = 100mv p-p frequenc y (mhz) ada4950-1, r l = 1k? ada4950-1, r l = 200? ada4950-2, a mp 1, r l = 1k? ada4950-2, a mp 1, r l = 200? ada4950-2, a mp 2, r l = 1k? ada4950-2, a mp 2, r l = 200? figure 19. 0.1 db flatness , small - signal frequency response for various loads ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 1 10 100 frequenc y (mhz) 1000 07957-020 v ocm gain (db) v ocm (ac) = 100mv p-p v ocm = ?2.5vdc v ocm = 0v v ocm = +2.5vdc figure 20. v ocm small - signal frequency response at various dc levels ?14 0 ? 13 0 ?12 0 ?11 0 ?10 0 ?9 0 ? 8 0 ?7 0 ?6 0 ?5 0 ?4 0 harmonic distortion (dbc) f r e q u e nc y ( m h z ) hd 2, r l, d m = 1k? hd 3, r l, d m = 1k? hd 2, r l, d m = 2 0 0? hd 3, r l, d m = 2 0 0? v o u t , dm = 2 v p-p 0. 1 1 1 0 10 0 07957-021 figure 21 . harmonic distortion vs. frequency at various loads ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 1 10 100 1000 closed-loop gain (db) ada4950-1, r l = 1k? ada4950-1, r l = 200? ada4950-2, amp 1, r l = 1k? ada4950-2, amp 1, r l = 200? ada4950-2, amp 2, r l = 1k? ada4950-2, amp 2, r l = 200? 07957-022 v ou t , dm = 2v p-p frequenc y (mhz) figure 22. 0.1 db flatness , large - signal frequency response for various loads ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 1 10 100 1000 07957-023 v ocm gain (db) v ocm (ac) = 2v p-p v ocm = ?2.5vdc v ocm = 0v v ocm = +2.5vdc frequenc y (mhz) figure 23. v ocm large - signal frequency response at various dc levels ?14 0 ? 13 0 ?12 0 ?11 0 ?10 0 ?9 0 ? 8 0 ?7 0 ?6 0 ?5 0 ?4 0 harmonic distortion (dbc) f r e q u e nc y ( m h z ) v o u t , dm = 2 v p-p 0. 1 1 1 0 10 0 hd2, g = 1 hd3, g = 1 hd2, g = 2 hd3, g = 2 hd2, g = 3 hd3, g = 3 07957-024 figure 24. harmonic distortion vs. frequency at various gains
ada4950- 1/ada4950 - 2 data s heet rev. b | page 12 of 26 ?14 0 ? 13 0 ?12 0 ?11 0 ?10 0 ?9 0 ? 8 0 ?7 0 ?6 0 ?5 0 ?4 0 harmonic distortion (dbc) f r e q u e nc y ( m h z ) v o u t , dm = 2 v p-p 0. 1 1 1 0 10 0 hd2, 5v hd3, 5v hd2, 2.5v hd3, 2.5v 07957-025 figure 25 . harmonic distortion vs. frequency at various supplies ?13 0 ?12 0 ?11 0 ?10 0 ?9 0 ?8 0 ? 7 0 ?6 0 ?5 0 ?4 0 ?3 0 ?4 ?3 ?2 ?1 0 1 2 3 4 h a r m o nic di s t o r t i o n (d bc) v o c m ( v ) v o u t , dm = 2 v p-p hd2 at 10mhz hd3 at 10mhz hd2 at 30mhz hd3 at 30mhz 07957-026 figure 26 . harmonic distortion vs. v ocm at various frequencies, 5 v supplies ?14 0 ? 13 0 ?12 0 ?11 0 ?10 0 ?9 0 ? 8 0 ?7 0 ?6 0 ?5 0 ?4 0 harmonic distortion (dbc) f re q ue nc y ( m hz ) hd 2, v out, dm = 2v p-p hd 3, v out, dm = 2v p-p hd 2, v out, dm = 4v p-p hd 3, v out, dm = 4v p-p 0. 1 1 1 0 10 0 07957-027 figure 27 . harmonic distortion vs. frequency at various v out, dm ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 harmonic distortion (dbc) v out, dm (v p-p) v ocm = 0v hd2, 5v hd3, 5v hd2, 2.5v hd3, 2.5v 07957-028 figure 28 . harmonic distortion vs. v out, dm , f = 10 mhz ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 harmonic distortion (dbc) v ocm (v) v out, dm = 2v p-p hd2 at 10mhz hd3 at 10mhz hd2 at 30mhz hd3 at 30mhz 07957-029 figure 29 . harmonic distortion vs. v ocm at various frequencies, 5 v supply ?14 0 ?12 0 ?13 0 ?11 0 ?10 0 ?9 0 ? 8 0 ?7 0 ?6 0 ?5 0 spurious-free dynamic range (dbc) f r e q u e nc y ( m h z ) v o u t , dm = 2 v p-p 0. 1 1 1 0 10 0 r l, d m = 2 0 0? r l, d m = 1k? 07957-030 figure 30 . spurious - free dynamic range vs. frequency at various loads
data sheet ada4950- 1/ada4950 - 2 rev. b | page 13 of 26 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 29.6 29.7 29.8 29.9 30.0 30.1 30.2 30.3 30.4 30.5 normalized spectrum (db) frequency (mhz) v out, dm = 2v p-p 07957-031 figure 31 . 30 mhz intermodulation distortion ?65 ?63 ?59 ?57 ?61 ?55 ?51 ?53 ?45 ?47 ?49 1 10 100 1000 cmrr (db) frequency (mhz) 07957-032 r l, dm = 200? v in = 2v p-p figure 32 . cmrr vs. frequency ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 1m 10m 100m 1g output balance (db) frequency (hz) v o ut, dm = 2v p-p 07957-033 figure 33 . output balance vs. frequency 80 ?80 ?60 ?40 ?20 0 20 40 60 90 ?270 ?225 ?180 ?135 ?90 ?45 0 45 1k 10k 100k 1m 10m 100m 1g 10g gain (db) phase (degrees) frequency (hz) gain phase 07957-240 figure 34 . open - loop gain and phase vs. frequency ?120 ?100 ?80 ?60 ?40 ?20 0 1 10 100 1000 psrr (db) frequency (mhz) psrr? psrr+ 07957-035 r l, dm = 200? v in, dm = 100mv p-p figure 35 . psrr vs. frequency ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 1 10 100 1000 crosstalk (db) frequency (mhz) amplifier 2 to amplifier 1 amplifier 1 to amplifier 2 07957-036 r l, dm = 200? v in, dm = 2v p-p figure 36 . crosstalk vs. frequency, ada4950 - 2
ada4950- 1/ada4950 - 2 data s heet rev. b | page 14 of 26 ?60 ?50 ?40 ?30 ?20 ?10 0 1 10 100 1000 s-parameters (db) frequency (mhz) 07957-037 r l, dm = 200? v in, dm = 100mv p-p input single-ended, 50? load termin a tion output differential, 100? source termin a tion s 1 1: single-ended- t o-single-ended s22: differential- t o-differentia l s11 s22 figure 37 . return loss (s 11 , s 22 ) vs. frequency 1 1 0 10 0 100 0 1 10 100 1k 10k 100k 1m 10m o u t p u t v o l t a g e n o i se d e n s i t y (n v / h z ) f r e q u e nc y ( h z ) 07957-038 g = 1 g = 2 g = 3 figure 38 . voltage noise spectral density for various gains, referred to out put ?0 . 0 6 ?0. 0 4 ?0 . 0 2 0 0 . 0 2 0 . 04 0 . 0 6 0 5 1 0 1 5 2 0 2 5 3 0 n o rm a l ize d output voltag e (v) t i m e ( n s) g = 1 g = 2 g = 3 07957-039 figure 39 . small - signal pulse response for various gains 0.1 1 10 100 1k 0.1 1 10 100 1k closed-loop output impedance magnitude (?) frequency (mhz) +out ?out v out, dm 07957-040 figure 40 . closed - loop output impedance magnitude vs. frequency, g = 1 15 10 5 0 ?5 ?10 ?15 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 07957-041 voltage (v) time (s) 2 v in v out, dm figure 41 . overdrive recovery, g = 2 ?1.5 ?1.0 ?0 . 5 0 0.5 1.0 1.5 0 5 1 0 1 5 2 0 2 5 3 0 n o rm a l ize d output voltag e (v) t i m e ( n s) 07957-042 g = 3 g = 2 g = 1 figure 42 . large - signal pulse response for various gains
data sheet ada4950- 1/ada4950 - 2 rev. b | page 15 of 26 ?0.10 ?0.05 0 0.05 0.10 0 5 10 15 20 2 5 30 output voltage (v) ti m e (n s) c l = 0pf c l = 0.9pf c l = 1.8pf c l = 2.7pf 07957-043 figure 43 . small - signal pulse response for various capacitive loads ?0 .0 6 ?0. 0 4 ?0 .0 2 0 0 .0 2 0. 04 0 .0 6 0 5 1 0 1 5 2 0 2 5 3 0 output common-mode voltage (v) ti m e ( n s) 07957-044 figure 44 . v ocm small - signal pulse response ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 ?5 0 5 10 15 20 25 30 35 40 error (%) voltage (v) time (ns) output input error 07957-045 figure 45 . settling time ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 0 5 10 15 20 25 30 output voltage (v) time (ns) c l = 0pf c l = 0.9pf c l = 1.8pf c l = 2.7pf 07957-046 figure 46 . large - signal pulse response for various capacitive loads ?1.5 ?1.0 ?0.5 0.5 0 1.0 1.5 0 5 10 15 20 25 30 output common-mode voltage (v) time (ns) 07957-047 figure 47 . v ocm large - signal pulse response ?1 1 0 2 3 4 5 6 ?0.2 0.2 0 0.4 0.6 0.8 1.0 1.2 0 1 2 3 4 5 6 7 8 noninverting output voltage (v) pd pin voltage (v) time (ms) 07957-048 pd pin input (shown inverted for clarity) v ocm = +1v dc figure 48 . pd response time
ada4950-1/ada4950-2 data sheet rev. b | page 16 of 26 test circuits ada4950-x 1k? +5 v 500? 500? 50? 500? 500? v ocm 53.6 ? v in 0.1f ?5v 250? nc 250? nc 25.5 ? dc-coupled source 07957-049 figure 49. equivalent basic test circuit, g = 1 ada4950-x +5v 500 ? 500 ? 500 ? 500 ? v ocm 56.2 ? ?5v 250 ? 49.9 ? 49.9 ? nc 250 ? differential network analyzer source differential network analyzer receiver nc 56.2 ? 50 ? 50 ? 07957-051 49.9 ? 49.9 ? figure 50. test circuit for output balance, cmrr ada4950-x 261? 442? ct 200? 2:1 442? 0.1f 0.1f +5 v 500? 500 ? 50 ? 500 ? 500? v ocm 53.6 ? v in 0.1f ?5v 250 ? nc 250 ? nc 25.5 ? dc-coupled low-pass filter source 07957-252 dual filter 50? figure 51. test circuit for distortion measurements
data sheet ada4950- 1/ada4950 - 2 rev. b | page 17 of 26 terminology +in ?in +out ?out +ina +inb ?inb ?ina v ocm r ga 500? v out, dm r l, dm ada4950-x 07957-152 r gb 250? r gb 250? r f 500? r f 500? r ga 500? figure 52 . signal and circuit definitions differential voltage differential voltage refers to the difference between two node voltages. for example, the output differential voltage (or eq uiv - alently, output differential n ode voltage) is defined as v out, dm = ( v +out ? v ?out ) where v +out and v ?out refer to the voltages at the +out and ?out output terminals with respect to a commo n ground reference. t he input differen tial voltage is defined in different ways, depending upon the selected gain. for g = 1 v in, dm = ( + ina ? ( ? ina )) where +ina and ? ina refer to the voltages at the + ina and ? ina input terminals with respect to a commo n ground reference ( input terminals +inb and ? inb are floating ) . for g = 2 v in, dm = ( + inb ? ( ? inb )) where +inb and ? inb refer to the voltages at the + inb and ? inb input terminals with respect to a commo n ground reference ( input terminals +ina and ? ina are floating ) . for g = 3 , input terminals +ina and +inb are connected together, and input terminals ? ina and ? inb are connected together . v in, dm = ( + inab ? ( ? inab )) where + inab and ? inab refer to the voltages at the connection of input terminals +ina and + inb and at the connection of input terminals ? ina and ? inb with respect to a commo n ground reference . common - mode voltage common - mode voltage refers to the average of two node voltages with respect to the local ground reference. the output common - mode voltage is defined as v out, cm = ( v +out + v ?out )/2 output balance output balance is a measure of how close the output differential signals are to being equal in amplitude and opposite in phase. any imbalances in amplitude or phase produce an undesired common - mode signal at the amplifier output. output balance error is defined as the magnitude of the output common - mode voltage divided by the magnitude of the output differential mode voltage. dm out cm out v v error balance output , , ? ? =
ada4950-1/ada4950-2 data sheet rev. b | page 18 of 26 theory of operation the ada4950-x differs from conventi onal op amps in that it has two outputs whose voltages move in opposite directions and an additional input, v ocm . like an op amp, it relies on high open-loop gain and negative feedback to force these outputs to the desired voltages. the ada4950-x behaves much like a standard voltage feedback op amp and facilitates single-ended-to-differential conversions, common-mode level shifting, and amplifications of differential signals. like an op amp, the ada4950-x has high input impedance at its internal input terminals (to the right of the internal gain resistors) and low output impedance. because it uses voltage feedback, the ada4950-x manifests a nominally constant gain bandwidth product. two feedback loops are used to control the differential and common-mode output voltages. the differential feedback loop, set with on-chip feedback and gain resistors, controls only the differential output voltage. the common-mode feedback loop is internal to the actual amplifier and controls only the common- mode output voltage. this architecture makes it easy to set the output common-mode level to any arbitrary value within the specified limits. the output common-mode voltage is forced, by the internal common-mode feedback loop, to be equal to the voltage applied to the v ocm input. the internal common-mode feedback loop produces outputs that are highly balanced over a wide frequency range without requiring tightly matched external components. this results in differential outputs that are very close to the ideal of being identical in amplitude and that are exactly 180 apart in phase.
data sheet ada4950- 1/ada4950 - 2 rev. b | page 19 of 26 applications information analyzing an applica tion circuit the ada4950 - x uses high open - loop gain and negative feedback to force its differential and common - mode output voltages in such a way as to minimize the differential and common - mode error voltages. the differential error voltage is defined as the voltage between the dif ferential inputs labeled +in x and ?in x (see figure 52 ). for most purposes, this voltage can be assumed to be 0 . similarly, the difference between the actual output c ommon - mode voltage and the voltage applied to v ocm can also be assumed to be 0 . starting from these principles , any application circuit can be analyzed. se lect ing the closed - loop gain using the approach described in the analyzing an application circuit section , the differential gain of the circuit in figure 52 can be determined b y g f dm in dm out r r v v = , , where the input resistors ( r g ) and the feedback resistors ( r f ) on each side are equal. for g = 1 , the +ina and ? ina inputs are used, and the +inb and ? inb inputs are left floating. the differential gain in this case is calculated as follows : 1 500 500 = ? ? = = g f r r g for g 2 , te +inb and ? inb inputs are used, and te +ina and ? ina inputs are let loatin te dierential ain in tis case is calculated as ollos 2 2 = ? ? = = g f r r g for g , te +ina and +inb inputs are con nected toeter, and te ? ina and ? inb inputs are connected toeter te dierential ain in tis case is calculated as ollos 2 = ? ? ? = = g f r r g estimating the outpu t noise voltage the differential output noise of the ada4950 - x can be estimated using the noise model in figure 53. the values of r g depend on the selected gain. the input - referred noise voltage density, v nin , is modeled as a differential input , and the noise currents, i nin? and i nin+ , appear between each input and ground. the output voltage due to v nin is obtained by multiplying v nin by the noise gain, g n (defined in the g n equation that follows table 13) . t he noise currents are uncorrelated with the same mean - square value, and each produce s an output voltage that is equal to the noise current multiplied by the associated feedback resistance . the noise voltage density at the v ocm pin is v ncm . when the feedback networks have the same feedback factor , as is true in most cases, the output noise due to v ncm is common mode. each of the four resistors contributes (4ktr x x ) 1/2 . the noise from the fee dback resistors appears directly at the output, and the noise from the gain resistors appears at the output multiplied by r f /r g . table 11 summarizes the input noise sources, the multiplication factors, and the output - referred noise density terms. ada4950-x + r f2 v nod v ncm v ocm v nin r f1 r g2 r g1 v nrf1 v nrf2 v nrg1 v nrg2 i nin+ i nin? 07957-053 figure 53 . noise model t able 11 . output noise voltage density calculations for matched feedback networks input noise contribution input noise term input noise voltage density output multiplication factor differential output noise voltage density term differential input v nin v nin g n v no1 = g n ( v nin ) inverting input i nin ? i nin ? ( r f2 ) 1 v no2 = ( i nin ? )(r f 2 ) noninverting input i nin + i nin + ( r f1 ) 1 v no3 = ( i nin + )(r f1 ) v ocm input v ncm v ncm 0 v no4 = 0 v gain resistor , r g1 v nrg1 (4ktr g1 ) 1/2 r f1 /r g1 v no5 = (r f1 /r g1 ) (4ktr g1 ) 1/2 gain resistor , r g2 v nrg2 (4ktr g2 ) 1/2 r f2 /r g2 v no6 = (r f2 /r g2 ) (4ktr g2 ) 1/2 feedback resistor , r f1 v nrf1 (4ktr f1 ) 1/2 1 v no7 = (4ktr f1 ) 1/2 feedback resistor , r f2 v nrf2 (4ktr f2 ) 1/2 1 v no8 = (4ktr f2 ) 1/2
ada4950- 1/ada4950 - 2 data s heet rev. b | page 20 of 26 table 12 . differential input, dc - coupled nominal linear gain r f ( ) r g ( ) r in, dm ( ) differential output noise density (nv/hz) 1 500 500 1000 9.25 2 500 250 500 12.9 3 500 250||500 333 16.6 table 13 . single - ended, ground - referenced input, dc - coupled, r s = 50 ? nominal linear gain r f ( ) r g1 ( ) r t ( ) (std 1%) r in, se ( ) r g2 ( ) 1 differential output noise density (nv/hz) 1 500 500 53.6 667 526 9.07 2 500 250 57.6 375 277 12.2 3 500 250||500 61.9 267 194 15.0 1 r g2 = r g1 + (r s ||r t ). similar to the case of a conventional op amp, the output noise voltage densities can be estimated by multiplying the input - referred terms at +in x and ?in x by the appropriate output factor, where: ( ) 2 1 n g + = 2 is the circuit noise gain. g1 f1 g1 1 r r r + = g2 f2 g2 2 r r r + = g f n r r g + = = 1 1 note that the output noise from v ocm goes to 0 in this case. the total differential output noise density, v nod , is the root - sum - square of the individual output noise terms. = = 8 1 i 2 noi nod v v tale 12 and tale 1 list te tree availale ain settins, associated resistor values, input impedance , and output noise densit or ot alanced and unalanced input coniurations calculating the inpu t impedance for an application circuit the effective input impedance of a circuit depends on whether the amplifier is being driven by a single - ended or dif ferential signal source. for balanced differential input signals, as shown in figure 54 , the input impedance (r in, dm ) is r in, dm = ( r g + r g ) = 2 r g the value of r g depends on the selected gain. +v s ?v s +in ?in r f r f v ocm r g r g v out, dm v in, dm 07957-054 ada4950-x figure 54 . ada4950 - x configured for balanced (differential) inputs for an unbalanced, single - ended input signal (see figure 55 ), the input impedance is ( ) ? ? ? ? ? ? ? ? ? ? ? ? + ? = f g f g se in r r r r r 2 1 , ada4950-x r l v out, dm +v s ?v s r g r g r f r f v ocm r in, se 07957-055 figure 55 . ada4950 - x with unbalanced (single - ended) input the input impedance of the circuit is effectively higher than it is for a conventional op amp connected as an inverter because a fraction of the differential output voltage appears at the inputs as a common - mode signal, partially bootstrapping the voltage across the input resistor , r g . the common - mode voltage at the ampli fier input terminals can be easily determined by noting that the voltage at the inverting input is equal to the non inverting output voltage divided down by the voltage divider that is formed by r f and r g in the lower loop. this voltage is present at both input terminals due to negative voltage feedback and is in phase with the input signal, thus reducing the effective voltage across r g in the upper loop and partially bootstrapping r g .
data sheet ada4950- 1/ada4950 - 2 rev. b | page 21 of 26 terminating a single - ended input this section d escribes how to properly terminate a single - ended input to the ada4950 - x with a gain of 1 , r f = 500 ? , and r g = 500 ? . a n e xample using an input source with a terminated output voltage of 1 v p - p and source resistance of 50 ? illustrates the steps that must be followed. n ote that because the terminated output voltage of the source is 1 v p - p , the open - circuit output voltage of the source is 2 v p - p . the source shown in figure 56 indicates this open - circuit voltage. 1. the input impedance is calculated using the f ollowing f or mula: 667 ) 500 500 ( 2 500 1 500 ) ( 2 1 , = ? ? ? ? ? ? ? ? ? ? ? ? + ? = ? ? ? ? ? ? ? ? ? ? ? ? + ? = f g f g se in r r r r r r s ? v s 2v p-p r in, se ? ada4950-x r l v out, dm +v s ?v s r g ? r g ? r f ? r f ? v ocm 07957-156 figure 56 . calculating single - ended input impedance , r in 2. t o match the 50 ? source resistance , calculate the termina tion resistor, r t , using r t ||667 ? = 50 ? . the closest standard 1% value for r t is 53.6 ?. ada4950-x r l v out, dm +v s v s r s r g r g r f r f v ocm v s 2v p-p r in, se r t 53.6 07957-157 figure 57 . adding t ermination r esistor , r t 3. figure 57 shows that the effective r g in the upper feedback loop is now greater than the r g in the lower loop due to the addition of the termination resistors. to comp ensate for the imbalance of the gain resistors , add a correction resistor (r ts ) in series with r g in the lower loop . r ts is the thevenin e quivalent of the source resistance , r s , and the termination resistance , r t , and is equal to r s ||r t . r ts = r th = r s ||r t = 25.9 ? r s v s 2v p-p r t 53.6 r th v th 1.03v p-p 07957-052 figure 58 . calculating the thevenin equivalent note that v th is greater than 1 v p - p , which w as obtained with r t = 50 ? . the modified circuit with the thevenin equivalent (closest 1% value used for r th ) of the terminated source and r ts in the lower feedback loop is shown in figure 59. ada4950-x r l v out, dm +v s v s r th r g r g r f r f v ocm v th 1.03v p-p r ts 25.5 07957-059 figure 59 . thevenin equivalent and matched gain resistors figure 59 prese nts a tractable circuit with matched feedback loops that can be easily evaluated. it is useful to point out two effects that occur with a terminated input. the first is that the value of r g is increased in both loops, lowering the overall closed - loop gain. the second is that v th is a little larger than 1 v p - p , as it would be if r t = 50 ?. these two effects have opposite impacts on the output voltage , and for large resistor values in the feedback loops (~1 k? ), the effects essentially cancel each other out . for small r f and r g , or high gains, however, the diminished closed - loop gain is not canceled completely by the increased v th . this can be seen by evaluating figure 59. the desired differential output in this example i s 1 v p - p becaus e the terminated input signal is 1 v p - p a nd the closed - loop gain = 1 . the actual differential output voltage, however, is equal to (1.0 3 v p - p ) (500 / 525 .5 ) = 0.98 v p - p .
ada4950-1/ada4950-2 data sheet rev. b | page 22 of 26 input common-mode voltage range the ada4950-x input common-mode voltage range is shifted down by approximately one v be , in contrast to other adc drivers with centered input ranges such as the ada4939-x. the downward-shifted input common-mode range is especially suited to dc-coupled, single-ended-to-differential, and single- supply applications. for 5 v operation, the input common-mode voltage range at the summing nodes of the amplifier is specified as ?4.8 v to +3.2 v. with a 5 v supply, the input common-mode voltage range at the summing nodes of the amplifier is specified as +0.2 v to +3.2 v. to avoid nonlinearities, the voltage swing at the +inx and ?inx terminals must be confined to these ranges. input and output capacitive ac coupling although the ada4950-x is well suited to dc-coupled applica- tions, it is nonetheless possible to use it in ac-coupled circuits. input ac coupling capacitors can be inserted between the source and r g . this ac coupling blocks the flow of the dc common- mode feedback current and causes the ada4950-x dc input common-mode voltage to equal the dc output common-mode voltage. the ac coupling capacitors must be placed in both loops to keep the feedback factors matched. output ac coupling capacitors can be placed in series between each output and its respective load. input signal swing considerations the input terminals of fully differential amplifiers with external gain and feedback resistors connect directly to the amplifier summing nodes; the common-mode voltage swing at these terminals is generally smaller than the input and output swings. in most linear applications, the summing node voltages do not approach levels that result in the forward-biasing of the internal esd protection diodes on the amplifier inputs. signals at the inputs of the ada4950-x are applied to the input side of the gain resistors, and, if caution is not exercised, these signals can be large enough to forward-bias the esd protection diodes. the four inputs that make up the differential signal paths each have four esd diodes in series to the negative supply and one diode to the positive supply; the v ocm input has one esd diode to each supply. figure 60 illustrates the esd protection circuitry. ada4950-x + v s ?v s 500 ? 500 ? 500 ? 500 ? 250 ? v ocm 250 ? 07957-253 1 4 1 4 1 4 1 1 1 4 figure 60. input esd pr otection circuitry setting the output common-mode voltage the v ocm pin of the ada4950-x is internally biased with a vol- tage divider comprising two 50 k resistors across the supplies, with a tap at a voltage approximately equal to the midsupply point, [(+v s ) + (?v s )]/2. because of this internal divider, the v ocm pin sources and sinks current, depending on the externally applied voltage and its associated source resistance. relying on the internal bias results in an output common-mode voltage that is within approximately 100 mv of the expected value. in cases where more accurate control of the output common- mode level is required, it is recommended that an external source or resistor divider be used with source resistance less than 100 . if an external voltage divider consisting of equal resistor values is used to set v ocm to midsupply with greater accuracy than produced internally, higher values can be used because the external resistors are placed in parallel with the internal resistors. the input v ocm offset listed in the specifications section assumes that the v ocm input is driven by a low impedance voltage source. it is also possible to connect the v ocm input to a common-mode level (cml) output of an adc; however, care must be taken to ensure that the output has sufficient drive capability. the input impedance of the v ocm pin is approximately 10 k to a voltage of nominally midsupply. if multiple ada4950-x devices share one adc reference output, a buffer may be necessary to drive the parallel inputs.
data sheet ada4950-1/ada4950-2 rev. b | page 23 of 26 layout, grounding, and bypassing as a high speed device, the ada4950-x is sensitive to the pcb environment in which it operates. realizing its superior performance requires attention to the details of high speed pcb design. the first requirement is a solid ground plane that covers as much of the board area around the ada4950-x as possible. the thermal resistance, ja , is specified for the device, including the exposed pad, soldered to a high thermal conductivity 4-layer circuit board, as described in eia/jesd51-7. bypass the power supply pins as close to the device as possible and directly to a nearby ground plane. use high frequency ceramic chip capacitors. it is recommended that two parallel bypass capacitors (1000 pf and 0.1 f) be used for each supply. place the 1000 pf capacitor closer to the device. farther away, provide low frequency bulk bypassing using 10 f tantalum capacitors from each supply to ground. signal routing should be short and direct to avoid parasitic effects. wherever complementary signals exist, provide a symmetrical layout to maximize balanced performance. when routing differential signals over a long distance, keep pcb traces close together, and twist any differential wiring to minimize loop area. doing this reduces radiated energy and makes the circuit less susceptible to interference. 1.30 0.80 0.80 1.30 07957-056 figure 61. recommended pcb thermal attach pad (dimensions in millimeters) 0.30 plated via hole 1.30 ground plane power plane bottom metal top metal 07957-057 figure 62. cross-section of 4-layer pcb showing thermal via co nnection to buried ground plane (dimensions in millimeters)
ada4950-1/ada4950-2 data sheet rev. b | page 24 of 26 high performance adc driving the ada4950-x is ideally suited for broadband dc-coupled applications. the circuit in figure 63 shows a front-end connection for an ada4950-1 driving an ad9245 adc, with dc coupling on the ada4950-1 input and output. (the ad9245 achieves its optimum performance when driven differentially.) the ada4950-1 eliminates the need for a transformer to drive the adc and performs a single-ended-to- differential conversion and buffering of the driving signal. the ada4950-1 is configured with a single 3.3 v supply and a gain of 2 for a single-ended input to differential output. the 57.6 termination resistor, in parallel with the single-ended input impedance of 375 , provides a 50 termination for the source. the additional 26.7 thevenin resistance added to the inverting input balances the parallel impedance of the 50 source and the termination resistor driving the noninverting input. the required thevenin bias voltage of 0.27 vdc applied to the lower loop is obtained by scaling the vref output of the ad9245 and buffering it with the ad8031. in this example, the 50 signal generator has a 1 v p-p unipolar open-circuit output voltage, and 0.5 v p-p output voltage when terminated in 50 . the v ocm input is bypassed for noise reduc- tion and set externally with 1% resistors to maximize output dynamic range on the tight 3.3 v supply. because the inputs are dc-coupled, dc common-mode current flows in the feedback loops, and a nominal dc level of 0.76 v is present at the amplifier input terminals. a fraction of the output signal is also present at the input terminals as a common-mode signal; its level is equal to the ac output swing at the noninverting output, divided down by the feedback factor of the lower loop. in this example, this ripple is 0.5 v p-p [276.7/(276.7 + 500)] = 0.18 v p-p. this ac signal is riding on the 0.76 v dc level, producing a voltage swing between 0.67 v and 0.85 v at the input terminals. this is well within the specified limits of 0.2 v to 1.5 v. with an output common-mode voltage of 1.65 v, each ada4950-1 output swings between 1.4 v and 1.9 v, opposite in phase, provid- ing a gain of 2 and a 1 v p-p differential signal to the adc input. the differential rc section between the ada4950-1 output and the adc provides single-pole low-pass filtering and extra buffering for the current spikes that are output from the adc input when its sha capacitors are discharged. the ad9245 is configured for a 1 v p-p full-scale input by connecting its sense pin to vref, as shown in figure 63. 33? 33? 50? 57.6 ? 0.1f 20pf vin? vin+ agnd avdd ad9245 vref sense 10f + 0.1f v out, dm = 1v p-p v out, cm = +1.65v 1.0v p-p unipolar signal source ada4950-1 +3.3 v 500? 500? 500? 500? 250 ? nc 250? nc 26.7 ? 0.1f 0v 1.0v 0.5v v ocm 10k? 10k? 0.1f 0.1f 866? 1.0k ? 0.1f ad8031 0.1f 10f + 07957-254 figure 63. ada4950-1 driving an ad9245 adc with unipolar dc-coupled input and output, gain = 2
data sheet ada4950- 1/ada4950 - 2 rev. b | page 25 of 26 outline dimensions 1.45 1.30 sq 1.15 111808-a 1 0.50 bsc bot t om view top view 16 5 8 9 12 13 4 exposed pa d pin 1 indic a t or 3.10 3.00 sq 2.90 0.50 0.40 0.30 sea ting plane 0.05 max 0.02 nom 0.20 ref 0.25 min coplanarity 0.08 pin 1 indic a t or 0.30 0.23 0.18 compliant to jedec standards mo-220-weed. for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.80 0.75 0.70 figure 64 . 16 - lead lead f rame chip scale package [lfcsp_w q] 3 mm 3 mm body, very very thin quad (cp - 16 - 21 ) dimensions shown in millimeters 0.50 bsc 0.50 0.40 0.30 compliant to jedec standards mo-220-wggd-8. bot t om view top view 4.10 4.00 sq 3.90 sea ting plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.203 ref coplanarity 0.08 pin 1 indic a t or 1 24 7 12 13 18 19 6 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 01-18-2012- a 0.30 0.25 0.20 pin 1 indic a t or 0.20 min 2.40 2.30 sq 2.20 exposed pa d figure 65 . 24 - lead lead frame chip scale package [lfcsp _ w q] 4 mm 4 mm body , very very thin quad (cp - 24 - 14 ) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ordering quantity branding ada4950 - 1ycpz -r2 ?40c to +105c 16- lead lfcsp_w q cp -16-2 1 250 h1l ada4950 - 1ycpz -rl ?40c to +105c 16- lead lfcsp_w q cp -16-2 1 5,000 h1l ada4950 - 1ycpz -r7 ?40c to +105c 16- lead lfcsp_w q cp -16-2 1 1,500 h1l ada4950 - 1ycp - ebz evaluation board ada4950 - 2ycpz -r2 ?40c to + 10 5c 24- lead lfcsp_w q cp -24-1 4 250 ada4950 - 2ycpz -rl ?40c to + 10 5c 24- lead lfcsp_w q cp -24-1 4 5 , 000 ada4950 - 2ycpz -r7 ?40c to + 10 5c 24- lead lfcsp_w q cp -24-1 4 1 , 500 ada4950 - 2ycp - ebz evaluation board 1 z = rohs compliant part.
ada4950- 1/ada4950 - 2 data sheet rev. b | page 26 of 26 notes ? 2009 C 2015 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d07957 - 0- 10/15(b)

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